Shanghai, China – March 2, 2026 – Cadence (NASDAQ: CDNS) today announced the launch of the ChipStack™ AI Super Agent, an agentic AI solution for front-end chip design and verification, marking a transformative step in redefining semiconductor design methodologies. As the world's first agentic workflow for automated chip design and verification, ChipStack AI Super Agent delivers up to a 10x productivity gain in code design, simulation environment setup, test plan creation, regression test orchestration, and debug and auto-fix.

'ChipStack represents a significant leap forward in our design-for-AI and AI-for-design strategy,' said Anirudh Devgan, president and CEO of Cadence. 'By applying agentic AI directly to our customers' front-end design flows, we are addressing the growing complexity and scale challenges of modern chips. Leveraging intelligent agents that can autonomously invoke underlying tools, we deliver substantial productivity gains on critical design and verification tasks, allowing scarce engineering talent to focus on innovation.'

The new ChipStack AI Super Agent embodies the Cadence Intelligent System Design™ vision, seamlessly combining AI orchestration, physics-based simulation, and accelerated computing to deliver transformative solutions for semiconductor and systems innovation. This agentic AI solution orchestrates multiple virtual engineers, all running on Cadence's core EDA tools. The technology combines agentic AI with Cadence's proven optimization AI and AI assistant solutions, which have been used in over 1,000 tapeouts to date, including the Verisium™ verification platform and Cadence Cerebrus intelligent chip explorer, as well as the Cadence JedAI data and AI platform.

ChipStack AI Super Agent flexibly supports cutting-edge models for both cloud and on-premises deployment, including open-source NVIDIA Nemotron models customizable via NVIDIA NeMo, as well as cloud-hosted models (such as OpenAI GPT), enhancing designer productivity. This further advances the vision of a true 'Silicon Agent' that spans the multi-disciplinary and multi-workflow requirements of delivering next-generation intelligent devices.